The present invention relates to read/write circuitry of a magnetic storage system. In particular, the present invention relates to a low-power read/write preamplifier configured for interconnection with a magnetic head in the magnetic storage system.
Magnetic storage systems store information by magnetizing adjacent bit positions on a recording surface of a magnetic media, such as a magnetic disk in a magnetic disk drive. Within the magnetic disk drive, an actuator arm supports a magnetic head close to the disk surface for reading and writing information to the disk surface. In larger storage systems, disk drives include several disks stacked upon one another. An actuator assembly supports several actuator arms. Each arm supports a magnetic head near the recording surface of its respective disk.
The magnetic head includes an inductive coil which reads and writes information by sensing or creating a changing magnetic field. For example, in write mode, the magnetic head writes information by forcing a relatively large current through the inductive coil in a selected direction to polarize a bit position adjacent the magnetic head in the selected direction. By controlling the direction at which adjacent bit positions are polarized, digital information may be written onto the disk surface.
In read mode, the inductive coil senses changes in polarization of adjacent bit positions. The changes in polarization induce a current in the inductive coil in a direction indicative of the direction at which the adjacent bit positions are polarized. The direction of the induced current is therefore representative of the data stored on the disk.
A read/write preamplifier controls read and write operations of the magnetic heads. The preamplifier includes one head cell circuit for each magnetic head. The head cell circuits are connected together in parallel to the rest of the read/write preamplifier circuitry. Each head cell circuit includes both read circuitry and write circuitry connected to an inductive coil. The read circuitry monitors or senses the direction of current flow induced in the inductive coil during read mode. The write circuitry controls the direction of current flow through the inductive coil during write mode.
During read mode, the read circuitry monitors the direction of current flow induced in the inductive coil at the head contacts. The read circuitry typically includes a read differential transistor pair, connected between a read current sink and a read amplifier. Each transistor in the pair includes a control terminal connected to the head contacts. Differential voltages at the head contacts are indicative of the direction of induced current through the inductive coil. These differential voltages drive the transistors in the read differential transistor pair between ON and OFF states. Current flow through the read pair is therefore representative of the data stored on the disk surface.
During write mode, the write control circuitry forces a relatively large current through the inductive coil which creates a magnetic field that polarizes the adjacent bit position on the disk surface. The write control circuitry controls the direction at which current flows through the inductive coil to polarize the bit position adjacent the inductive coil in either a first direction or in a second direction, opposite the first direction.
The write control circuitry typically includes an H-switch used to control the direction of current flow through the coil. The H-switch includes upper write switching transistors and lower write switching transistors. The upper write switching transistors are connected between a first supply rail and the head contacts. The lower write switching transistors are connected between the head contacts and a second supply rail through a write current sink. The write control circuitry controls the direction of current flow through the inductive coil by driving selected transistors in the H-switch between ON and OFF states. The write control circuitry applies a maximum voltage swing across the head contacts for reversing current flow and polarizing the adjacent bit position.
Only a single head is selected at a given time. Because the read circuitry for all heads are connected in parallel, extraneous signals from any head cell write control circuitry can corrupt the read signals. Therefore, the head cell circuitry of the unselected heads is powered down by selection circuitry to prevent unwanted signals from being written to or read from the magnetic disk. The read circuitry is powered down during write mode by removing the read current sink. The write control circuitry is powered down during read mode by removing the drive for the control terminals of the upper write switching transistors and by inactivating the write current sink. The drive for the upper write switching transistors is removed through a voltage bias circuit which biases the control terminals of the upper write switching transistors. This effectively creates a high impedance connection between the write control H-switch and the head contacts, thereby isolating the write control circuitry from the magnetic head and from the read circuitry. This allows the H-switch transistors to float to a lower voltage level at the head contacts, preventing interference with the relatively small read signals.
The voltage bias circuitry for one known Hswitch includes an NPN-type transistor for controlling drive current into the control terminals of the upper write switching transistors. A mode controlled current sink is connected to a control terminal of the NPN-type transistor. When the mode controlled current sink is active (during the unselected states and read mode), it pulls a relatively large current through a bias resistor to pull the control terminal to a LOW state to switch the NPN-type transistor into an OFF state. When the mode controlled current sink is inactive (during the selected state and write mode), the bias resistor pulls the control terminal of the NPN-type transistor to a HIGH state causing the NPN-type transistor to turn ON and conduct current. In the ON state, the NPN-type transistor supplies drive current to the control terminals of the upper write switching transistors. In the OFF state, the NPN-type transistor removes drive current from the upper write switching transistors causing the transistors to form high impedance connections with the head contacts.
In large storage systems, with ten heads for example, considerable power is dissipated in the nine unselected heads for removing the drive to the upper write switching transistors. Power dissipation is a critical design concern for circuits of this type, particularly for applications with extremely low power requirements. Therefore, a read/write preamplifier having a biasing circuit that removes drive current from the upper write switching transistors with minimal power is desired.